Semiconductor memory cells can generally be classified into two groups--high speed operation and large memory capacity. Attaining high speed operation usually incurs the use of bipolar devices which inevitably results in a large amount of power consumption. One example of a bipolar high speed memory is utilizing emitter coupled logic (ECL). It is difficult to obtain large memory capacity on a semiconductor chip utilizing bipolar techniques in the memory cell due to power consumption limitations. When design constraints require a large memory capacity, MOS devices are normally utilized for both the memory cell and the various peripheral circuits. However, MOS devices have a great deal of capacitance associated with the various nodes in addition to larger voltage swings than some bipolar technologies such as ECL. To attain this larger memory capacity with the use of MOS devices usually requires a sacrifice in the operating speed of the memory.
Bipolar transistors have been utilized in high speed semiconductor memories due to their low impedance characteristics which allows them to operate at the higher speeds. Typically, a memory cell for a high speed bipolar memory utilizes cross-coupled NPN transistors with PNP load transistors. This is conventionally termed a "cross-coupled SCR" memory cell. This configuration has provided the optimum performance choice for a number of years. The use of the PNP load provides both a smaller cell layout and a higher noise margin than other bipolar configurations. The larger noise margin is due to the gain of the PNP load. However, one disadvantage of this device is that both the NPN and PNP devices are in hard saturation, resulting in a slow reverse recovery time when turning off. This directly increases the write recovery time.
Attempts to improve the write recovery time have utilized techniques to reduce the lifetimes of holes injected into the epitaxial layer of the transistors. However, these techniques have been unsatisfactory in that they result in a larger cell area with the requirement of additional implants and circuit adjustments to maintain temperature tracking. Therefore, a need exists to reduce the recovery time of the NPN transistors in the SCR cross-coupled latch without substantially increasing the cell size or incurring any temperature tracking problems.